
DS1205S
021798 8/17
MOVE BLOCK
Figure 12
WRITE 64–BIT
PASSWORD
OF DESTINATION
SUBKEY
TERMINATE
TRANSACTION
NO
YES
WRITE MOVE BLOCK IN
COMMAND WORD
IS DATA =
PARTITION
PASSWORD
TRANSFER SPECIFIED
SCRATCHPAD DATA BLOCKS
TO SPECIFIED PARTITION
ERASE ALL
SCRATCHPAD MEMORY
TERMINATE TRANSACTION
WRITE 64–BIT BLOCK
SELECTOR CODE
TO DS1205
*
*
*
TRANSPARENT TO USER
3-WIRE BUS
The 3-wire bus is comprised of three signals. These are
the RST (reset) signal, the CLK (clock) signal, and the
DQ (data) signal. All data transfers are initiated by driv-
ing the RST input high. The RST signal provides a meth-
od of terminating a data transfer.
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, the data must be valid
during the rising edge of a clock cycle. Command bits
and data bits are input on the rising edge of the clock and
data bits are output on the falling edge of the clock. All
data transfers terminate if RST is low and the DQ pin
goes to a high impedance state. When data transfers to
the DS1205S are terminated by the RST signal going
low, the transition of the RST going low must occur dur-
ing a high level of the CLK signal. Failure to ensure that
the CLK signal is high will result in the corruption of the
last bit transferred. Data transfers are illustrated in
Figure 13 and Figure 14 for normal modes of operation.