PART NUMBER DELAY TABLE (tPLH, t
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鍨嬭櫉锛� DS1135LZ-15+
寤犲晢锛� Maxim Integrated Products
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鎻忚堪锛� IC DELAY LINE 15NS 8-SOIC
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Lead (SnPb) Finish for COTS
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鐛ㄧ珛寤堕伈鏁�(sh霉)锛� 3
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宸ヤ綔婧害锛� -40°C ~ 85°C
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灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SOIC
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DS1135L
2 of 7
LOGIC DIAGRAM Figure 1
PART NUMBER DELAY TABLE (tPLH, tPHL) Table 1
PART NUMBER
DELAY PER
OUTPUT
(ns)
INITIAL
TOLERANCE
(Note 1)
TOLERANCE OVER
TEMP AND VOLTAGE
(Note 2)
0掳C to +70掳C
-40掳C to +85掳C
DS1135LZ-10+
10/10/10
1.0ns
卤2
.0ns
卤3.0
ns
DS1135LZ-12+
12/12/12
1.0ns
卤2
.0ns
卤3.0
ns
DS1135LZ-15+
15/15/15
1.0ns
卤2
.5ns
卤4.0
ns
DS1135LZ-20+
20/20/20
1.0ns
卤2
.5ns
卤4.0
ns
DS1135LZ-25+
25/25/25
1.5ns
卤3.0
ns
卤5.0
ns
DS1135LZ-30+
30/30/30
1.5ns
3.0ns
卤5.0
ns
+Denotes a lead(Pb)-free/RoHS-compliant package.
NOTES:
1. Nominal conditions are +25掳C and VCC = +3.3V.
2. Voltage range of 2.7V to 3.6V.
3. Delay accuracies are for both leading and trailing edges.
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1135L.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected to the output. The DS1135L output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
TIME DELAY
OUT
IN
ONE OF THREE
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