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參數(shù)資料
| 型號： | DS1099U-PR+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ECONOSCILLATOR DUAL 8USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | EconOscillator™ |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 無 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 127.9Hz，31.98Hz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1099
Low-Frequency Dual EconOscillator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
The divider settings, X0 and X1, are factory pro-
grammed. When placing an order for the DS1099, it is
required to specify X0 and X1. If only one output is used,
it is recommended that the unused output be disabled.
The oscillator outputs are asynchronous. Since the
master oscillator and dividers are free running, even
when both outputs are disabled, the state of the output
when OE becomes active is unknown for up to half an
fOUT period. When OE is brought low, the output is
enabled instantaneously. Likewise, if the output is dis-
abled while outputting the low half of a cycle, the out-
put instantaneously is forced high before the current
cycle is completed.
Application Information
Power-Supply Decoupling
To achieve best results, it is highly recommended that
a decoupling capacitor is used on the IC power-supply
pins. Typical values of decoupling capacitors are
0.01F and 0.1F. Use a high-quality, ceramic, sur-
face-mount capacitor, and mount it as close as possi-
ble to the VCC and GND pins of the IC to minimize lead
inductance.
Chip Topology
TRANSISTOR COUNT: 4221
SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Revision History
Pages changed at Rev 1: 1, 2, 3, 5, 6
Ordering Information (continued)
ααα
α
DIVISOR
fOUT
A2
0
1.048MHz
B2
1
0.524MHz
C2
2
0.262MHz
D2
3
0.131MHz
E2
4
65.50kHz
F2
5
32.750kHz
G2
6
16.375kHz
H2
7
8.187kHz
J2
8
4.093kHz
K2
9
2.046kHz
L2
10
1.023kHz
M2
11
511.7Hz
N2
12
255.8Hz
P2
13
127.9Hz
Q2
14
63.96Hz
R2
15
31.98Hz
S2
16
16Hz
T2
17
8Hz
U2
18
4Hz
W2
19
2Hz
X2
20
1Hz
Y2
21
0.5Hz
Z2
22
0.25Hz
Branding Information
The package branding includes
α0 and α1 on the top
of the package next to or below 1099.
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