掳C to +85掳C; VCC= " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� DS1077Z-120+
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 8/21闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ECONOSCILLATOR 120MHZ 8SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 100
绯诲垪锛� EconOscillator™
椤炲瀷锛� 鎸暕鍣�锛屽浐瀹氶牷鐜囷紙闆欒矾锛�
闋荤巼锛� 14.6kHz ~ 120MHz
闆绘簮闆诲锛� 4.75 V ~ 5.25 V
闆绘祦 - 闆绘簮锛� 50mA
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
鍖呰锛� 绠′欢
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
DS1077
16 of 21
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(-40
掳C to +85掳C; VCC= 5V卤5%)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX UNITS NOTES
Fast Mode
400
SCL Clock Frequency
f
SCL
Standard Mode
100
kHz
Fast Mode
1.3
Bus Free Time
Between a STOP
and START Condition
t
BUF
Standard Mode
4.7
s
Fast Mode
0.6
Hold Time (Repeated)
START Condition
t
HD
:STA
Standard Mode
4.0
s
6
Fast Mode
1.3
LOW Period of SCL
t
LOW
Standard Mode
4.7
s
Fast Mode
0.6
HIGH Period of SCL
t
HIGH
Standard Mode
4.0
s
Fast Mode
0.6
Set-Up Time for a
Repeated START
t
SU
:STA
Standard Mode
4.7
s
Fast Mode
0
Data Hold Time
t
HD
:DAT
Standard Mode
0
0.9
s
7,8
Fast Mode
100
Data Set-Up Time
t
SU
:DAT
Standard Mode
250
ns
Fast Mode
300
Rise Time of Both
SDA and SCL Signals
t
R
Standard Mode
20 + 0.1
C
B
1000
ns
9
Fast Mode
Fall Time of Both SDA
and SCL Signals
t
F
Standard Mode
20 + 0.1
C
B
300
ns
9
Fast Mode
0.6
Set-Up Time For STOP
t
SU
:STO
Standard Mode
4.0
s
Capacitive Load for
Each Bus Line
C
B
400
pF
9
Input Capacitance
C
I
5
pF
NONVOLATILE MEMORY CHARACTERISTICS
PARAMETER
SYMBOL CONDITION
MIN
TYP
MAX
UNITS NOTES
Writes
+85C
10,000
NOTES:
1) All voltages are referenced to ground.
2) 8.13kHz is obtained from a -66MHz standard part.
3) PDN is a power-down signal applied to either CTRL0 or CTRL1 pins as appropriate.
4) Output voltage swings may be impaired at high frequencies combined with high output loading.
5) After this period, the first clock pulse is generated.
6) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7) The maximum t
HD
:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
鐩搁棞(gu膩n)PDF璩囨枡
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DS1077Z-120+ 鍔熻兘鎻忚堪:鍙法绋嬫尟钑╁櫒 EconOscillator/Dvdr 120MHz 118mil 2-Wire RoHS:鍚� 鍒堕€犲晢:IDT 灏佽 / 绠遍珨:5 mm x 7 mm x 1.5 mm 闋荤巼:15.476 MHz to 866.67, 975 MHz to 1300 MHz 闋荤巼绌�(w臎n)瀹氭€�:+/- 50 PPM 闆绘簮闆诲:3.63 V 璨�(f霉)杓夐浕瀹�:10 pF 绔帴椤炲瀷:SMD/SMT 杓稿嚭鏍煎紡:LVPECL 鏈€灏忓伐浣滄韩搴�:- 40 C 鏈€澶у伐浣滄韩搴�:+ 85 C 灏哄:7 mm W x 5 mm L x 1.5 mm H 灏佽:
DS1077Z-120+T&R 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:ECO OSC 120MHZ 2-WIRE 8P-SO TRL LF - Tape and Reel 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC ECONOSCILLATOR 120MHZ 8-SOIC
DS1077Z-120+T&R 鍔熻兘鎻忚堪:鍙法绋嬫尟钑╁櫒 EconOscillator/Dvdr 120MHz 118mil 2-Wire RoHS:鍚� 鍒堕€犲晢:IDT 灏佽 / 绠遍珨:5 mm x 7 mm x 1.5 mm 闋荤巼:15.476 MHz to 866.67, 975 MHz to 1300 MHz 闋荤巼绌�(w臎n)瀹氭€�:+/- 50 PPM 闆绘簮闆诲:3.63 V 璨�(f霉)杓夐浕瀹�:10 pF 绔帴椤炲瀷:SMD/SMT 杓稿嚭鏍煎紡:LVPECL 鏈€灏忓伐浣滄韩搴�:- 40 C 鏈€澶у伐浣滄韩搴�:+ 85 C 灏哄:7 mm W x 5 mm L x 1.5 mm H 灏佽:
DS1077Z-125 鍔熻兘鎻忚堪:鍙法绋嬫尟钑╁櫒 EconOscillator/Dvdr 125MHz 118mil 2-Wire RoHS:鍚� 鍒堕€犲晢:IDT 灏佽 / 绠遍珨:5 mm x 7 mm x 1.5 mm 闋荤巼:15.476 MHz to 866.67, 975 MHz to 1300 MHz 闋荤巼绌�(w臎n)瀹氭€�:+/- 50 PPM 闆绘簮闆诲:3.63 V 璨�(f霉)杓夐浕瀹�:10 pF 绔帴椤炲瀷:SMD/SMT 杓稿嚭鏍煎紡:LVPECL 鏈€灏忓伐浣滄韩搴�:- 40 C 鏈€澶у伐浣滄韩搴�:+ 85 C 灏哄:7 mm W x 5 mm L x 1.5 mm H 灏佽:
DS1077Z-125+ 鍔熻兘鎻忚堪:鍙法绋嬫尟钑╁櫒 EconOscillator/Dvdr 125MHz 118mil 2-Wire RoHS:鍚� 鍒堕€犲晢:IDT 灏佽 / 绠遍珨:5 mm x 7 mm x 1.5 mm 闋荤巼:15.476 MHz to 866.67, 975 MHz to 1300 MHz 闋荤巼绌�(w臎n)瀹氭€�:+/- 50 PPM 闆绘簮闆诲:3.63 V 璨�(f霉)杓夐浕瀹�:10 pF 绔帴椤炲瀷:SMD/SMT 杓稿嚭鏍煎紡:LVPECL 鏈€灏忓伐浣滄韩搴�:- 40 C 鏈€澶у伐浣滄韩搴�:+ 85 C 灏哄:7 mm W x 5 mm L x 1.5 mm H 灏佽: