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參數(shù)資料
| 型號： | DS1065T-80 |
| 英文描述： | IC-OSC/DIVIDER |
| 中文描述： | IC-OSC/DIVIDER |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 207K |
| 代理商： | DS1065T-80 |
DS1065
4 of 10
1
X
X
INTERNAL OSCILLATOR DIVIDED BY 1
DIV WORD
Figure 3
(MSB)
(LSB)
N (9-BITS)
N
These 9 bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
BIT
VALUES
000000000
000000001
.
.
.
.
.
111111111
DIVISOR (N)
VALUE
2
3
.
.
.
.
.
513
POWER-ON RESET
When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar
to that which occurs when the device is restored from a power-down condition. This sequence comprises
two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period
to allow the oscillator to reach a stable frequency before enabling the output:
1.
Initialize internal circuitry.
2.
Enable internal oscillator.
3.
Set M and N to maximum values.
4.
Wait approximately 1024 cycles of INTOSC for the oscillator to stabilize.
5.
Load M and N programmed values from EEPROM.
6.
Enable OUT.
Figure 10
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