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參數(shù)資料
| 型號： | DS1023 |
| 英文描述： | 8-Bit Programmable Timing Element |
| 中文描述： | 8位、可編程定時單元 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 261K |
| 代理商： | DS1023 |
DS1023
3 of 16
Applications can read the setting of the DS1023 Delay Line by connecting the serial output pin (Q) to the
serial input (D) through a resistor with a value of 1 to 10 kohms (Figure 2). Since the read process is
destructive, the resistor restores the value read and provides isolation when writing to the device. The
resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a
daisy chain (Figure 1). For serial readout with automatic restoration through a resistor, the device used to
write serial data must go to a high impedance state.
To initiate a serial read, latch enable (LE) is taken to a logic 1 while serial clock (CLK) is at a logic 0.
After a waiting time (t
EQV
), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 --> 1)
transition of the serial clock (CLK), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time
t
CQV
. To restore the input register to its original state, this clocking process must be repeated eight times.
In the case of a daisy chain, the process must be repeated eight times per package. If the value read is
restored before latch enable (LE) is returned to logic 0, no settling time (t
EDV
) is required and the
programmed delay remains unchanged.
Since the DS1023 is a CMOS design, unused input pins (P3 - P7) must be connected to well-defined logic
levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.
CASCADING MULTIPLE DEVICES (DAISY CHAIN)
Figure 1
SERIAL READOUT
Figure 2
REFERENCE DELAY
In all delay lines there is an inherent, or “step zero”, delay caused by the propagation delay through the
input and output buffers. In this device the step zero delay can be quite large compared to the delay step
size. To simplify system design a reference delay has been included on chip which may be used to
compensate for the step zero delay. In practice this means that if the device is supplied with a clock, for
example, the minimum programmed output delay is effectively zero with respect to the reference delay.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1033-8 | 3-in-1 Low Voltage Silicon Delay Line |
| DS1033 | 3-in-1 Low Voltage Silicon Delay Line |
| DS1033-10 | MB 16C 16#16 SKT PLUG |
| DS1033-12 | MB 39C 37#20 2#16 SKT PLUG |
| DS1033-15 | MB 41C 41#20 SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1023-025 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:8-Bit Programmable Timing Element |
| DS1023-050 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:8-Bit Programmable Timing Element |
| DS1023-100 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS1023-200 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:8-Bit Programmable Timing Element |
| DS1023-500 | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
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