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參數(shù)資料
| 型號： | DS1021S-50 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.300 INCH, SOIC-16 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 193K |
| 代理商： | DS1021S-50 |
DS1021
8 of 9
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the corresponding output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1021S-50/T&R | 制造商:Maxim Integrated Products 功能描述:IC DEL LN 256TAP 137.5NS 16SOIC |
| DS1021S-50/T&R | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1021S-50+ | 功能描述:延遲線/計(jì)時(shí)元素 Programmable 8-Bit .5ns Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1021S-50+T&R | 制造商:Maxim Integrated Products 功能描述:IC DEL LN 256TAP 137.5NS 16SOIC |
| DS1021S-50+T&R | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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