參數(shù)資料
型號: DS1021S-25/T&R
廠商: Maxim Integrated Products
文件頁數(shù): 8/9頁
文件大?。?/td> 0K
描述: IC DELAY LINE 256TAP 16-SOIC
標(biāo)準(zhǔn)包裝: 1,000
標(biāo)片/步級數(shù): 256
功能: 可編程
延遲到第一抽頭: 10ns
接頭增量: 0.25ns
可用的總延遲: 73.75ns
獨立延遲數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
DS1021
8 of 9
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the corresponding output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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參數(shù)描述
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DS1021S-50+ 功能描述:延遲線/計時元素 Programmable 8-Bit .5ns Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube
DS1021S-50+T&R 制造商:Maxim Integrated Products 功能描述:IC DEL LN 256TAP 137.5NS 16SOIC