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參數(shù)資料
| 型號： | DS1020-50 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AA, DIP-16 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 255K |
| 代理商： | DS1020-50 |
DS1020
8 of 9
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS10-20B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 20 |
| DS1020G-025 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| DS1020G-050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| DS1020G-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
| DS1020G-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Delay Line |
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