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參數(shù)資料
| 型號(hào)： | DS1012 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 2-in-1 Sub-Miniature Silicon Delay Line with Logic(片內(nèi)集成2個(gè)獨(dú)立的帶邏輯的硅超小型延遲線) |
| 中文描述： | 2合1小微型硅延遲線（片內(nèi)集成2個(gè)具有邏輯獨(dú)立的帶邏輯的硅超小型延遲線） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 53K |
| 代理商： | DS1012 |
DS1012
2-in-1 Sub-Miniature Silicon
Delay Line with Logic
DS1012
021798 1/7
FEATURES
All-silicon time delay
53
μ
W max. CMOS quiescent mode
Surface mount 8-pin mini-SOIC and standard 8-pin
DIP
2 independent buffered delays per input
Option of complemented output(s)
Option of timed AND, NAND, OR, NOR, XOR, XNOR,
HALF-XOR and HALF-XNOR logic outputs
Delay tolerance:
±
1.5 ns (delays: 3-10 ns),
±
2.0 ns (delays: 11-40 ns)
Vapor phase, IR and wave solderability
Economical
TTL/CMOS-compatible
Quick turn prototypes
Custom delays and logic options available
PIN ASSIGNMENT
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
GND
OUT1
OUT3
IN1
V
CC
IN2
OUT2
OUT4
GND
OUT1
OUT3
IN1
V
CC
IN2
OUT2
OUT4
DS1012M 8-PIN DIP (300 MIL)
See Mech. Drawings
Section
DS1012Z 8-PIN SOIC (150 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
IN1, IN2
OUT1, OUT2
OUT3, OUT4
GND
V
CC
– Inputs
– Outputs (delays)
– Outputs (delays, logic)
– Ground
– +5 Volts
DESCRIPTION
In its most simple configuration, the DS1012 2-in-1
Sub-Miniature Silicon Delay Line Chip provides two in-
puts, each of which in turn provides independent delays
to a pair of outputs. The DS1012-1 and DS1012-3 are
examples of catalog parts having this basic configura-
tion. Any of the four outputs can be inverted at the time
of manufacture.
For applications requiring two-input timed logic func-
tions, at the time of manufacture the simple delay on
OUT4 can be replaced by one of the following: OR,
NOR, XOR, or XNOR. Similarly, a timed AND, NAND,
HALF-XOR (D3 AND D4), or NOT HALF-XOR (D3 OR
D4) can be substituted for the simple delay on OUT3.
DS1012-2, DS1012-4, and DS1012-5 are examples of
catalog parts configured with logic functions on OUT3
and OUT4. Note that DS1012-2 also utilizes an output
inversion on OUT2.
In any configuration, delays D1 (t
D1
) and D2 (t
D2
) can be
specified within the range of ~3 ns to 10 ns. Delays D3
(t
D3
) and D4 (t
D4
) can be specified to have values be-
tween ~3 ns and 40 ns. The worst case leading edge
delay accuracy at nominal voltage and room tempera-
ture is
±
2 ns. The DS1012 is offered in two packages: an
8-pin DIP and an 8-pin 150 mil wide mini-SOIC.
Dallas Semiconductor offers the DS1012 in a wide vari-
ety of custom delay and logic configurations. For special
requests and quick turn delivery, call (972) 371–4348.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS10-12B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 12 |
| DS1012H1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| DS1012H2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| DS1012H3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| DS1012H4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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