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參數(shù)資料
| 型號： | DS1010S-75 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.300 INCH, SOIC-16 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 60K |
| 代理商： | DS1010S-75 |
DS1010
5 of 6
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
相關PDF資料 |
PDF描述 |
|---|---|
| DS1010-350 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1010-450 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1010-400 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1010-150 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1010-175 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1010S-75/T&R | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1010S-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| DS-1011 | 制造商:Molex 功能描述: |
| DS10-12B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 12 |
| DS1012H1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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