- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1992 > DS1010S-50+T&R (Maxim Integrated Products)IC DELAY LINE 10TAP 16-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | DS1010S-50+T&R |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 4/6闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DELAY LINE 10TAP 16-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,000 |
| 妯�(bi膩o)鐗�/姝ョ礆(j铆)鏁�(sh霉)锛� | 10 |
| 鍔熻兘锛� | 涓嶅彲绶ㄧ▼ |
| 寤堕伈鍒扮涓€鎶介牠锛� | 5ns |
| 鎺ラ牠澧為噺锛� | 5ns |
| 鍙敤鐨勭附寤堕伈锛� | 50ns |
| 鐛�(d煤)绔嬪欢閬叉暩(sh霉)锛� | 1 |
| 闆绘簮闆诲锛� | 4.75 V ~ 5.25 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 甯跺嵎 (TR) |
DS1010
4 of 6
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25掳C. Input-to-tap delays accurate on both rising and falling edges within 卤2 ns or 卤5%
whichever is greater.
4. See 鈥淭est Conditions鈥� section.
5. For DS1010 delay lines with a TAP 10 delay of 100 ns or greater, temperature variations from 25
掳C
to 0
掳C or 70掳C may produce an additional input-to-tap delay shift of 卤2ns or 卤3%, whichever is
greater.
6. For DS1010 delay lines with a TAP 10 delay less than 100 ns, temperature variations from 25
掳C to
0
掳C or 70掳C may produce an additional input-to-tap delay shift of 卤1 ns or 卤9%, whichever is greater.
7. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP
1 slows down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
8. Pulse width and period specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
9. Certain high-frequency applications not recommended for -50 in 16-pin package. Consult factory.
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| DS1013S-25+T&R | IC DELAY LINE 25NS 16-SOIC |
| DS1020S-50+T | IC DELAY LINE 256TAP 16-SOIC |
| DS1021S-50+T&R | IC DELAY LINE 256TAP 16-SOIC |
| DS1023S-25+W | IC DELAY LINE 256TAP 16-SOIC |
| DS1033Z-8+W | IC DELAY LINE 8NS 8-SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS1010S-60 | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
| DS1010S-60/T&R | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC DELAY LINE 10TAP 60NS 16SOIC |
| DS1010S-60/T&R | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
| DS1010S-75 | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
| DS1010S-75/T&R | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
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