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參數(shù)資料
| 型號： | DS1010S-50+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 10TAP 16-SOIC |
| 標準包裝： | 45 |
| 標片/步級數(shù)： | 10 |
| 功能： | 不可編程 |
| 延遲到第一抽頭： | 5ns |
| 接頭增量： | 5ns |
| 可用的總延遲： | 50ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 管件 |
DS1010
5 of 6
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1010S-50/T&R | 制造商:Maxim Integrated Products 功能描述:IC DELAY LINE 10TAP 50NS 16SOIC |
| DS1010S-50/T&R | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1010S-50/T&R/701 | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1010S-50+ | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1010S-50+T&R | 制造商:Maxim Integrated Products 功能描述:IC DELAY LINE 10TAP 50NS 16SOIC |
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