參數(shù)資料
型號: DS1010G-75
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Delay Line
英文描述: SILICON DELAY LINE, TRUE OUTPUT, PDIP14
封裝: 0.300 INCH, DIP-14
文件頁數(shù): 8/14頁
文件大?。?/td> 1392K
代理商: DS1010G-75
DS1010
3 of 6
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-1.0V to +7.0V
Operating Temperature
0
°C to 70°C
Storage Temperature
-55
°C to +125°C
Soldering Temperature
260
°C for 10 seconds
Short Circuit Output Current
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER
SYM
TEST
CONDITION
MIN
TYP
MAX
UNITS
NOTES
Supply Voltage
VCC
4.75
5.00
5.25
V
1
High Level Input
Voltage
VIH
2.2
VCC + 0.5
V
1
Low Level Input
Voltage
VIL
-0.5
0.8
V
1
Input Leakage
Current
II
0.0V
≤ V
I
≤ V
CC
-1.0
1.0
A
Active Current
ICC
VCC=Max;
Period=Min.
40
150
mA
2
High Level Output
Current
IOH
VCC=Min.
VOH=4
-1.0
mA
Low Level Output
Current
IOL
VCC=Min.
VOL=0.5
12
mA
AC ELECTRICAL CHARACTERISTICS
(TA = 25°C; VCC = 5V ± 5%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Pulse Width
tWI
40% of TAP 10 tPLH
ns
8
Input to Tap Delay
(leading edge)
tPLH
Table 1
ns
3, 4, 5, 6,
7, 9
Input to Tap Delay
(trailing edge)
tPHL
Table 1
ns
3, 4, 5, 6,
7, 9
Power-up Time
tPU
100
ms
Period
4 (tWI)ns
8
CAPACITANCE
(TA = 25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
510
pF
相關(guān)PDF資料
PDF描述
DS1013G-100 SILICON DELAY LINE, TRUE OUTPUT, PDIP14
DS1013G-25 SILICON DELAY LINE, TRUE OUTPUT, PDIP14
DS1013G-50 SILICON DELAY LINE, TRUE OUTPUT, PDIP14
DS1013H-25 SILICON DELAY LINE, TRUE OUTPUT, PDIP8
DS1013H-50 SILICON DELAY LINE, TRUE OUTPUT, PDIP8
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