參數(shù)資料
型號(hào): DS1010-80
廠商: Maxim Integrated Products
文件頁數(shù): 5/6頁
文件大?。?/td> 0K
描述: IC DELAY LINE 10TAP 80NS 14-DIP
標(biāo)準(zhǔn)包裝: 25
標(biāo)片/步級(jí)數(shù): 10
功能: 不可編程
延遲到第一抽頭: 8ns
接頭增量: 8ns
可用的總延遲: 80ns
獨(dú)立延遲數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 14-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 14-PDIP
包裝: 管件
DS1010
5 of 6
TEST CIRCUIT Figure 3
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
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