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參數(shù)資料
| 型號： | DS100BR111SQ/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REPEATER 10.3GBPS 2CH 24LLP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | * |
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SNLS338E – JANUARY 2011 – REVISED FEBRUARY 2013
Pin Descriptions(1)
Pin Name
Pin Number
I/O, Type
Pin Description
Differential High Speed I/O's
INA+, INA- ,
24, 23
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A on-chip 50
Ω
INB+, INB-,
11, 12
termination resistor connects INx+ to VDD and INx- to VDD.
OUTA+, OUTA-,
7, 8
O,CML
Inverting and non-inverting 50
Ω driver outputs with de-emphasis. Compatible with AC
OUTB+, OUTB-,
20, 19
coupled CML inputs.
Control Pins
ENSMB
3
I, LVCMOS
System Management Bus (SMBus) enable pin
Float
Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
ENSMB = 1 (SMBUS MODE)
SCL
5
I, LVCMOS
ENSMB Master or Slave mode
O, Open
SMBUS clock input pin is enabled. A clock input in Slave mode. Can also be a clock
Drain
output in Master mode.
SDA
4
I, LVCMOS,
ENSMB Master or Slave mode
O, Open
The SMBus bidirectional SDA pin is enabled. Data input or open drain (pull-down only)
Drain
output.
AD0-AD3
10, 9, 2, 1
I, LVCMOS,
ENSMB Master or Slave mode
Float
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus
(4-Levels)
slave address inputs. There are 16 addresses supported by these pins.
Pins must be tied LOW or HIGH when used to define the device SMBus address. (2)
READEN#
17
I, LVCMOS
When using an External EEPROM, a transition from high to low starts the load from
the external EEPROM
DONE#
18
IO,
EEPROM Download Status
LVCMOS,
HIGH indicates Error / Still Loading
Float
LOW indicates download complete. No Error.
(4-Levels)
ENSMB = 0 (PIN MODE)
EQA0, EQA1
10, 9
I, LVCMOS,
EQA/B ,0/1 control the level of equalization of each channel. The EQA/B pins are
EQB0, EQB1
1, 2
Float
active only when ENSMB is de-asserted (LOW).
(4-Levels)
When ENSMB goes high the SMBus registers provide independent control of each
lane, and the EQB0/B1 pins are converted to SMBUS AD2/AD3 inputs.
DEMA, DEMB
4, 5
IO,
DEMA/B controls the level of de-emphasis. The DEMA/B pins are only active when
LVCMOS,
ENSMB is de-asserted (LOW). Each of the 4 A/B channels have the same level
Float
unless controlled by the SMBus control registers. When ENSMB goes high the SMBus
(4-Levels)
registers provide independent control of each lane and the DEM pins are converted to
SMBUS SCL and SDA pins.
TX_DIS
6
I, LVCMOS
DS100BR111
High = OUTA Enabled /OUTB Disabled
Low = OUTA/B Enabled
VOD_SEL
17
I, LVCMOS,
EQ Mode and VOD select.
Float
High = 10G-KR Mode (VOD = 1.1V/1.3V)
(4-Levels)
Float = (VOD = 1.0 V)
20K = (VOD = 1.2 V)
Low = (VOD = 700m V)
VDD_SEL
16
I, Internal
Enables the 3.3V to 2.5V internal regulator
Pull-up
Low = 3.3 V Operation
Float = 2.5 V Operation
(1)
LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not guaranteed. Unless
the "Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V mode), or VIN (in 3.3V mode).Input
edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
(2)
Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = B0'h
(3)
DS100BR111 OUTA is limited to 700mV in pin mode.
4
Copyright 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS100BR111
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| DS100BR210EVK | 功能描述:其他開發(fā)工具 DS100BR210 EVAL BOARD RoHS:否 制造商:Parallax 產(chǎn)品:ELEV-8 Hex Upgrade Kits 類型:Robotics 工具用于評估:ELEV-8 Quadcopter 工作電源電壓: |
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| DS100BR210SQ/NOPB | 功能描述:IC REPEATER 10.3GBPS 2CH 24LLP RoHS:是 類別:集成電路 (IC) >> 接口 - 信號緩沖器，中繼器，分配器 系列:* 標(biāo)準(zhǔn)包裝:160 系列:- 類型:轉(zhuǎn)發(fā)器 Tx/Rx類型:以太網(wǎng) 延遲時(shí)間:- 電容 - 輸入:- 電源電壓:2.37 V ~ 2.63 V 電流 - 電源:60mA 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:托盤 其它名稱:Q5134101 |
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