- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄93255 > DS1005S-250/T&R (MAXIM INTEGRATED PRODUCTS INC) SILICON DELAY LINE, TRUE OUTPUT, PDSO16 PDF資料下載
參數(shù)資料
| 型號(hào)： | DS1005S-250/T&R |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.300 INCH, SO-16 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 62K |
| 代理商： | DS1005S-250/T&R |
DS1005
4 of 6
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25
°C. Delays accurate on both rising and falling edges within ±2 ns or ±3%, whichever
is greater.
4. See Test Conditions.
5. The combination of temperature variations from 25
°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of
±1.5 ns or
±4%, whichever is greater.
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows
down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1005M-125 | SILICON DELAY LINE, TRUE OUTPUT, PDIP8 |
| DS1005 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1007 | SILICON DELAY LINE, TRUE OUTPUT, PDIP16 |
| DS1010-125 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1010-200 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1005S-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| DS1005S-500 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Tapped Delay Line |
| DS1005S-60 | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1005S-60/T&R | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1005S-60+ | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。