2. VCC=5V and 25 " />
參數(shù)資料
型號: DS1004Z-4+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/6頁
文件大?。?/td> 0K
描述: IC DELAY LINE 5TAP 21NS 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
標(biāo)片/步級數(shù): 5
功能: 不可編程
延遲到第一抽頭: 5ns
接頭增量: 4ns
可用的總延遲: 21ns
獨立延遲數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
DS1004
5 of 6
NOTES:
1. All voltages are referenced to ground.
2. VCC=5V and 25
°C. Delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
°C ±=3°C
Supply Voltage (VCC):
5.0V
±=0.1V
Input Pulse:
High = 3.0V
±=0.1V
Low = 0.0V
±=0.1V
Source Impedance:
50 ohm max.
Rise and Fall Time:
3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width:
500 ns
Pulse Period:
1
s
Output Load
Capacitance:
15 pF
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
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