2. VCC=5V and 25 " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� DS1004Z-3+
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 5/6闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DELAY LINE 5TAP 17NS 8-SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 100
妯�(bi膩o)鐗�/姝ョ礆(j铆)鏁�(sh霉)锛� 5
鍔熻兘锛� 涓嶅彲绶ㄧ▼
寤堕伈鍒扮涓€鎶介牠锛� 5ns
鎺ラ牠澧為噺锛� 3ns
鍙敤鐨勭附寤堕伈锛� 17ns
鐛�(d煤)绔嬪欢閬叉暩(sh霉)锛� 1
闆绘簮闆诲锛� 4.75 V ~ 5.25 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SOIC
鍖呰锛� 绠′欢
DS1004
5 of 6
NOTES:
1. All voltages are referenced to ground.
2. VCC=5V and 25
掳C. Delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
掳C 卤=3掳C
Supply Voltage (VCC):
5.0V
卤=0.1V
Input Pulse:
High = 3.0V
卤=0.1V
Low = 0.0V
卤=0.1V
Source Impedance:
50 ohm max.
Rise and Fall Time:
3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width:
500 ns
Pulse Period:
1
s
Output Load
Capacitance:
15 pF
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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