- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9247 > DS1004Z-2+T (Maxim Integrated Products)IC DELAY LINE 5TAP 13NS 8-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | DS1004Z-2+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/6闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DELAY LINE 5TAP 13NS 8-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 妯�(bi膩o)鐗�/姝ョ礆(j铆)鏁�(sh霉)锛� | 5 |
| 鍔熻兘锛� | 涓嶅彲绶ㄧ▼ |
| 寤堕伈鍒扮涓€鎶介牠锛� | 5ns |
| 鎺ラ牠澧為噺锛� | 2ns |
| 鍙敤鐨勭附寤堕伈锛� | 13ns |
| 鐛�(d煤)绔嬪欢閬叉暩(sh霉)锛� | 1 |
| 闆绘簮闆诲锛� | 4.75 V ~ 5.25 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 甯跺嵎 (TR) |
DS1004
5 of 6
NOTES:
1. All voltages are referenced to ground.
2. VCC=5V and 25
掳C. Delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
掳C 卤=3掳C
Supply Voltage (VCC):
5.0V
卤=0.1V
Input Pulse:
High = 3.0V
卤=0.1V
Low = 0.0V
卤=0.1V
Source Impedance:
50 ohm max.
Rise and Fall Time:
3.0 ns max. (measured between 0.6V and 2.4V)
Pulse Width:
500 ns
Pulse Period:
1
s
Output Load
Capacitance:
15 pF
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VI-J74-MZ-S | CONVERTER MOD DC/DC 48V 25W |
| VI-B61-MY-F2 | CONVERTER MOD DC/DC 12V 50W |
| VI-B61-MY-F1 | CONVERTER MOD DC/DC 12V 50W |
| VI-J5K-MZ-S | CONVERTER MOD DC/DC 40V 25W |
| VI-B60-MY-F4 | CONVERTER MOD DC/DC 5V 50W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS1004Z-3 | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 5-Tap High-Speed Delay Line RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
| DS1004Z-3/T&R | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC DELAY LINE 5TAP 17NS 8SOIC |
| DS1004Z-3/T&R | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 5-Tap High-Speed Delay Line RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
| DS1004Z-3/W | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
| DS1004Z-3+ | 鍔熻兘鎻忚堪:寤堕伈绶�/瑷�(j矛)鏅�(sh铆)鍏冪礌 5-Tap High-Speed Delay Line RoHS:鍚� 鍒堕€犲晢:Micrel 鍔熻兘:Active Programmable Delay Line 鍌虫挱寤堕伈鏅�(sh铆)闁�:1000 ps 宸ヤ綔婧害鑼冨湇: 灏佽 / 绠遍珨:QFN-24 灏佽:Tube |
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