Virtex-E Ordering Information  
Revision History
The following table shows the revision history for this document. 
Figure 1:  
Ordering Information
Date
Version
Revision
12/7/99
1.0
Initial Xilinx release.
1/10/00
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL, 
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54, 
& 55, text explaining Table 5, T
BYP
 values, buffered Hex Line info, p. 8, I/O Timing 
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote 
references.
2/29/00
1.3
Updated pinout tables, V
CC
 page 20, and corrected Figure 20.
5/23/00
1.4
Correction to table on p. 22.
7/10/00
1.5
Numerous minor edits. 
Data sheet upgraded to Preliminary. 
Preview -8 numbers added to 
Virtex-E Electrical Characteristics
 tables. 
Reformatted entire document to follow new style guidelines. 
Changed speed grade
values in tables on pages 35-37. 
Min values added to 
Virtex-E Electrical Characteristics
 tables.
XCV2600E and XCV3200E numbers added to 
Virtex-E Electrical Characteristics
tables (Module 3).
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to 
“
No Connect in the XCV100E
“
 and removed duplicate V
CCINT
pins in Table ~ (Module 4). 
Changed pin J10 to 
“
No connect in XCV600E
”
 in Table 74 (Module 4).
Changed pin J30 to 
“
VREF option only in the XCV600E
”
 in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be 
“
AO in the XCV1000E, XCV1600E
“
.
8/1/00
1.6
9/20/00
1.7
Example: XCV300E-6PQ240C
Device Type
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
 I = Industrial (Tj = -40 C to +100 C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
Speed Grade
(-6, -7, -8)
DS022_043_072000