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| 型號： | DS_S1M8837 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | FRACTIONAL-N RF/INTEGER-N IF DUAL PLL |
| 中文描述： | 分?jǐn)?shù)N射頻/整數(shù)N如果雙鎖相環(huán) |
| 文件頁數(shù)： | 13/29頁 |
| 文件大?。?/td> | 234K |
| 代理商： | DS_S1M8837 |
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
13
Σ
-
modulator
The RF part of S1M8836/37 adopts the
Σ
-
modulator as a core of the fractional counter that makes it possible
to obtain divide ratio N to be a fractional number between two contiguous integers. The
Σ
-
modulator
effectively randomizes the quantization noise generated from digitizing process and results in extreme
suppression of in-band noise power by pushing it out to out-of-band as in conventional
Σ
-
data converter.
This technique eliminates the need for compensation current injection into the loop filter and improves fractional
spurious performance, suitable for high-tier applications.
The
Σ
-
modulator operates only for fractional-N mode, when the Frac-N_SEL is HIGH.
For proper use of the fractional mode, the user should be kept in mind that
1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976.
2.
For S1M8836/7, R can be selected 1-3. The clock frequency fixed at 9.84MHz (=19.68MHz/2, R=2) is
recommended for the
Σ
-
modulator which is an optimum condition for achieving good electrical
performances related to the fractional noise and power consumption. Only when using this clock frequency,
the S1M8836/37 guarantees the exact frequency resolutions: 10kHz for CDMA PCS and 30kHz for CDMA
cellular.
Note that the clock frequency much lower than 9.84MHz can deteriorate the fractional noise performance.
Users can use R=1 or R=3, too. For the case of R=1 or R=3, users must ask SAMSUNG for details.
Fractional noise performance may become better for R=1 (clock frequency=19.68MHz/1=19.68MHz). But the
RF operating frequency range may be shrinked for that case of R=1.
Phase-Frequency Detector (PFD) and Charge Pump (CP)
The RF/IF phase detector composed of PFD and CP outputs pump current into an external loop filter in
proportional to the phase difference between outputs of N and R counter. The phase detector has a better linear
transfer characteristic due to a feedback loop to eliminate dead zone. The polarity of the PFD can be
programmed using RF_PFD_POL/IF_PFD_POL depending on whether RF/IF VCO characteristics are positive or
negative. (Programmable descriptions for phase detection polarity)
Power-Down(or Power-Save) Control
Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits
(PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the
program control bits determine the state of power control. Power down forces all the internal blocks to be
deactivated and the charge pump output to be in the TRISTATE. The control register, however, remains active
for serial programming and is capable of loading and latching in data during the power down.
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