參數(shù)資料
型號(hào): DRM042
英文描述: Universal Serial Bus Wireless Optical Mouse and Multimedia Keyboard reference design designer reference manual
中文描述: 通用串行總線無(wú)線光學(xué)鼠標(biāo)和多媒體鍵盤(pán)參考設(shè)計(jì),設(shè)計(jì)參考手冊(cè)
文件頁(yè)數(shù): 74/80頁(yè)
文件大?。?/td> 1025K
代理商: DRM042
Glossary
Designer Reference Manual
DRMxxx — Rev 0.0
74
Glossary
MOTOROLA
H
— The upper byte of the 16-bit index register (H:X) in the CPU08.
H
— The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from the
low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required
for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction
uses the state of the H and C bits to determine the appropriate correction factor.
hexadecimal
— Base 16 numbering system that uses the digits 0 through 9 and the letters A through F.
high byte
— The most significant eight bits of a word.
illegal address
— An address not within the memory map
illegal opcode
— A nonexistent opcode.
I
— The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are
disabled.
index register (H:X)
— A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower
byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine
the effective address of the operand. H:X can also serve as a temporary data storage location.
input/output (I/O)
— Input/output interfaces between a computer system and the external world. A CPU
reads an input to sense the level of an external signal and writes to an output to change the level
on an external signal.
instructions
— Operations that a CPU can perform. Instructions are expressed by programmers as
assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and
instruction.
interrupt
— A temporary break in the sequential execution of a program to respond to signals from
peripheral devices by executing a subroutine.
interrupt request
— A signal from a peripheral to the CPU intended to cause the CPU to execute a
subroutine.
I/O
— See “input/output (I/0).”
IRQ
— See “external interrupt module (IRQ).”
jitter
— Short-term signal instability.
latch
— A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied
to the circuit.
latency
— The time lag between instruction completion and data movement.
least significant bit (LSB)
— The rightmost digit of a binary number.
logic 1
— A voltage level approximately equal to the input power voltage (V
DD
).
logic 0
— A voltage level approximately equal to the ground voltage (V
SS
).
low byte
— The least significant eight bits of a word.
low voltage inhibit module (LVI)
— A module that monitors power supply voltage.
LVI
— See “l(fā)ow voltage inhibit module (LVI).”
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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