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參數(shù)資料
| 型號： | DR8051 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-bit RISC Microcontroller ver 2.00 |
| 中文描述： | 8位RISC微控制器版本2.00 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 101K |
| 代理商： | DR8051 |
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
P I N S D E S C R I P T I O N
PIN
TYPE
DESCRIPTION
clk
input
Global clock
reset
input
Global synchronous reset
ramdatai[7:0]
input
Data bus from Internal Data Memory
sfrdatai[7:0]
input
Data bus from user SFRs
prgdatai[7:0]
input
Input data bus from Program Memory
xramdatai[7:0]
input
Data bus from External Data Memory
int0
input
External interrupt 0 line
int1
input
External interrupt 1 line
docddatai
input
DoCD data input
ramdatao[7:0]
output Data bus for Internal Data Memory
ramaddr[7:0]
output Internal Data Memory address bus
ramoe
output Internal Data Memory output enable
ramwe
output Internal Data Memory write enable
sfrdatao[7:0]
output Data bus for user SFRs
sfraddr[7:0]
output User SFRs address bus
sfroe
output User SFRs output enable
sfrwe
output User SFRs write enable
prgaddr[15:0]
output Program Memory address bus
prgdatao[7:0]
output Output data bus for Program Memory
prgdataz
output PRGDATA tri-state buffers control line
prgrd
output Program Memory read
prgwr
output Program Memory write
xramdatao[7:0]
output Data bus for External Data Memory
xramdataz
output XDATA tri-state buffers control line
xramaddr[23:0] output External Data Memory address bus
xramrd
output External Data Memory read
xramwr
output External Data Memory write
docddatao
output DoCD data output
docdclk
output DoCD clock line
pmm
output Power management mode indicator
stop
output Stop mode indicator
U N I T S S U M M A R Y
ALU
– Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder
– Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit
– Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface
– Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD module. Program fetch cycle length
can be programmed by user. This feature is
called Program Memory Wait States, and al-
lows core to work with different speed program
memories.
External Memory Interface
– Contains mem-
ory access related registers such as Data
Pointer High (DPH0), Data Pointer Low
(DPL0), Data Page Pointer (DPP0), MOVX
@Ri address register (MXAX) and STRETCH
registers. It performs the memory addressing
and data transfers. Allows applications soft-
ware to access up to 16 MB of external data
memory. The DPP0 register is used for seg-
ments swapping. STRETCH register allows
flexible timing management while accessing
different speed system devices by program-
ming XRAMWR and XRAMRD pulse width
between 1 – 8 clock periods.
Internal Data Memory Interface
– Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface
– Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller
– Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Power Management Unit
– Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Man-
agement Mode) to significantly reduce power
consumption.
Switchback
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
feature
allows
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