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參數(shù)資料
| 型號： | DR-11525FX-554Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | DIGITAL TO SYNCHRO OR RESOLVER, CDFP36 |
| 封裝： | CERAMIC, FLAT PACK-36 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 155K |
| 代理商： | DR-11525FX-554Z |
4
Data Device Corporation
www.ddc-web.com
DR-11525
G-06/05-0
Data Changing
Data Stable
50 nS min.
100 nS min.
50 nS min.
100 nS min.
200 nS min.
LL
LM
LA
DATA
Bits (9-16)
Bits (1-8)
200 nS min.
LA, LM, LL
Transparent = Hi
Latched = Lo
FIGURE 2B. LL,LM,LA TIMING DIAGRAMS (8 BIT)
200 nS min.
TRANSPARENT
LATCHED
DATA 1-16 BITS
50 nS min.
100 nS min.
Data Changing
Data Stable
FIGURE 2A. LL,LM,LA TIMING DIAGRAMS (16 BIT)
POWER SUPPLY CYCLING
Power supply cycling of the DDC converter should follow the
guidelines below to avoid any potential problems. Strictly main-
tain proper sequencing of supplies and signals per typical
CMOS circuit guidelines:
- Apply power supplies first (+15, -15V and ground).
- Apply digital control signals next.
- Apply analog signals last.
The reverse sequence should be followed during power down
of the circuit.
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