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參數(shù)資料
| 型號(hào)： | DPZ256X16IJ3-20B |
| 英文描述： | x16 Flash EEPROM Module |
| 中文描述： | x16閃存EEPROM模塊 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 992K |
| 代理商： | DPZ256X16IJ3-20B |
Dense-Pac Microsystems, Inc.
DPZ256X32IV3
The memory device internally generates a margin voltage and
applies it to the addressed location. If FFH is read from the
device, it indicates the location is erased. The erase/verify
command is issued prior to each location verification to latch
the address of the location to be verified. This continues until
FFH is not read from the device or the last address for the
device being erased is read.
If FFH is not read from the location being verified, an
additional erase operation is performed. Verification then
resumes from the last location verified. Once all locations in
the device being erased are verified, the erase operation is
complete. The verify operation should now be terminated by
writing a valid command such as program set-up to the
command register.
PRODUCT I.D. OPERATION:
The product I.D. operation outputs the manufacturer code
(89H) and the device code (B4H). This allows programming
equipment to match the device with the proper erase and
programming algorithms.
With CE and OE at a logic low level, raising A9 to V
(see
DC Operating Characteristics)
will initiate the operation. The
manufacturer’s code can then be read from address location
0000H and the device code can be read from address
location 0001H.
The I.D. codes can also be accessed via the command
register. Following a write of 90H to the command register,
a read from address location 0000H outputs the
manufacturer’s code (89H). A read from address location
0001H outputs the device code (B4H). To terminate the
operation, it is necessary to write another valid command into
the register.
POWER UP/DOWN PROTECTION:
The FLASH devices are designed to protect against accidental
erasure or programming during power transitions. It makes
no difference as to which power supply, V
or V
powers
up first. Power supply sequencing is not required. Internal
circuitry ensures that the command register is reset to the read
mode upon power up.
POWER SUPPLY DECOUPLING:
V
PP
traces should use trace widths and layout considerations
comparable to that of the V
power bus. The V
supply
traces should also be decoupled to help decrease voltage
spikes.
While the memory module has high-frequency,
low-inductance decoupling capacitors mounted on the
substrate connected to V
DD
and V
SS
, it is recommended that
a 4.7
μ
F to 10
μ
F electrolytic capacitor be placed near the
memory module connected across V
DD
and V
SS
for bulk
COMMAND DEFINITION TABLE
First Bus Cycle
Command
Bus
Cycles
Req’d
1
2
2
Second Bus Cycle
Operation
Address
Data
1
Operation
Address
Data
1
Read Memory
Setup Erase / Erase
Erase Verify
Write
Write
Write
X
X
EA
00H
20H
A0H
-
-
-
Write
Read
X
X
20H
EVD
Setup Program / Program
Program Verify
Reset
Read Product I.D. Codes
2
2
2
3
Write
Write
Write
Write
X
X
X
X
40H
C0H
FFH
90H
Write
Read
Write
Read
PA
X
X
IA
PD
PVD
FFH
ID
EA
EVD = Data Read from Location EA
IA
= Address: 0000H for manufacturing code, 0001H for device code
ID
= ID data read from IA during product ID operation
(Manufacturer = 89H, Device = B4H)
= Address to Verify
PA
PD = Data to be Programmed at Location PA
PVA = Data to be Read from Location PA at Program Verify
= Address to Program
TRUTH TABLE
WEn
OE
X
H
H
Mode
Description
Not Selected
Output Disable
Read
CEn
H
L
L
A0
X
X
A0
A9
X
X
A9
V
PP
V
PPLO
V
PPLO
V
PPLO
V
PPLO
V
PPLO
V
PPHI
V
PPHI
V
PPHI
V
PPHI
I/O Pins
HIGH-Z
HIGH-Z
D
OUT
Supply Current
Standby
Active
Active
READ
ONLY
X
H
L
I.D. (Mfr.)
I.D. (Device)
Not Selected
Output Disable
L
L
H
L
H
H
X
H
L
L
X
H
L
H
X
X
V
ID
V
ID
X
X
D
OUT
=89H
D
OUT
= B4H
HIGH-Z
HIGH-Z
Active
Active
Standby
Active
COMMAND
PROGRAM
Read
Write
L
L
H
L
L
H
A0
A0
A9
A9
D
OUT
D
IN
Active
Active
L = LOW, H = HIGH, X = Don’t Care
30A072-11
REV. A
3
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