參數(shù)資料
型號(hào): DP8441VLJ
英文描述: DRAM Controller
中文描述: DRAM控制器
文件頁(yè)數(shù): 18/46頁(yè)
文件大?。?/td> 644K
代理商: DP8441VLJ
5.0 Accessing Modes
(Continued)
TL/F/11718–41
FIGURE 12. Burst Read Access
Programming Selection
Bits
Mode
DTACK during Opening
R3
e
1, R2
e
0
3T
DTACK during Burst
R5
e
1, R4
e
0
2T
CAS Precharge during Burst
C9
e
0
Read:
(/2
T, Write: 1T
Column Address Counter Control
BO
e
0
DTACK Falling Edge
CAS and DTACK Edge Select
ECAS2
e
0
Falling Edge
18
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參數(shù)描述
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