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參數(shù)資料
| 型號： | DNC3X3425 |
| 廠商： | Lineage Power |
| 英文描述： | Quad 10/100 Mbits/s Ethernet Transceiver Macrocell(四通道10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 四10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（四通道1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 20/32頁 |
| 文件大小： | 757K |
| 代理商： | DNC3X3425 |
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20
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
4
Register Information
(continued)
Table 13. MR0—Control Register Bit Descriptions
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write, NA = not applicable.
Bit
*
Type
R/W
Description
0.15 (SW_RESET)
Reset.
Setting this bit to a 1 will reset the DNC3X3425. All registers will be set to
their default state. This bit is self-clearing. The default is 0.
Loopback.
When this bit is set to 1, no data transmission will take place on the
media. Any receive data will be ignored. The loopback signal path will contain all
circuitry up to, but not including, the PMD. The default value is a 0.
Speed Selection.
The value of this bit reflects the current speed of operation (1 =
100 Mbits/s; 0 = 10 Mbits/s). This bit will only affect operating speed when the auto-
negotiation enable bit (register 0, bit 12) is disabled (0). This bit is ignored when
autonegotiation is enabled (register 0, bit 12). This bit is ANDed with the
SPEED_PIN signal.
Autonegotiation Enable.
The autonegotiation process will be enabled by setting
this bit to a 1. The default state is a 1.
Powerdown.
The DNC3X3425 may be placed in a low-power state by setting this
bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver will be
powered down. While in the powerdown state, the DNC3X3425 will respond to
management transactions. The default state is a 0.
Isolate.
When this bit is set to a 1, the MII outputs will be brought to the high-
impedance state. The default state is a 0.
Restart Autonegotiation.
Normally, the autonegotiation process is started at pow-
erup. The process may be restarted by setting this bit to a 1. The default state is a
0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to a 1. This bit is
self-cleared when autonegotiation restarts.
Duplex Mode.
This bit reflects the mode of operation (1 = full duplex; 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is ORed with the
F_DUP pin.
Collision Test.
When this bit is set to a 1, the DNC3X3425 will assert the MCOL
signal in response to MTX_EN.
Reserved.
All bits will read 0.
0.14 (LOOPBACK)
R/W
0.13 (SPEED100)
R/W
0.12 (NWAY_ENA)
R/W
0.11 (PWRDN)
R/W
0.10 (ISOLATE)
R/W
0.9 (REDONWAY)
R/W
0.8 (FULL_DUP)
R/W
0.7 (COLTST)
R/W
0.6:0 (RESERVED)
NA
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