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參數(shù)資料
| 型號： | DMA2281 |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 496K |
| 代理商： | DMA2281 |
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DMA 2271, DMA 2280, DMA 2281
26
4.3.1. Control and Status Registers
Note: Not–used bits must be set to zero for control (receive) registers and are don’t care for status (transmit) registers.
Table 4–1:
16–bit DMA control registers, instructions from CCU to DMA
Address
Label
Bit No.
Default
Setting
Typical
Value
Function
14
14
14
VCOA
VCOS
DI1
DI2
DI3
0–7
8–10
11
14
15
0
4
0
0
4
0
VCO adjustment (range –128...+127)
alignment of the 20.25 MHz VCO
VCO select
1 = VCO3 selected
2 = VCO2 selected
4 = VCO1 selected
disable PLL output (pin 25, 26)
if (DI1 . or . DI2 . or DI3) then
PLL output = high impedance
23
23
SAV
SAU
2–7
10–15
32
32
25
18
saturation V adjust
0:
gain = 0
63: gain = 2
saturation U adjust
0:
gain = 0
63: gain = 2
200
200
200
LD
CTS
CT
3–7
8
10–15
4
0
32
6
1
16
luma delay adjust (range 0...30)
resolution: 20.25 MHz clock
luma contrast switch
luma contrast adjust
0:
gain = 0
63: gain = 1
63: gain = 2
if CTS = 1
if CTS = 0
201
201
201
201
201
201
201
DSY
DCL
DLC
NIN
PLLO
STA
CMP
0
1
2
3
4
5
6
1
0
0
0
0
0
0
0
0
0
0
0
0
0
disable sync outputs (pins 50–53, 58–60)
0 = enabled
1 = high impedance
disable clamping output (pin 48)
0 = enabled
1 = high impedance
disable luma/chroma output (pin 21–24, 27–38)
0 = enabled
1 = high impedance
non interlace
0 = interlace on
1 = interlace off
PLL open
0 = PLL closed
1 = PLL opened
stand alone operation
0 = digital insertion
1 = stand alone
chroma output multiplex
0 = 4 x 4 multiplex
1 = 2 x 8 multiplex
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