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參數資料
| 型號： | DM93L28 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual 8-Bit Shift Register(雙8位移位寄存器) |
| 中文描述： | 雙8位移位寄存器（雙8位移位寄存器） |
| 文件頁數： | 2/5頁 |
| 文件大?。?/td> | 41K |
| 代理商： | DM93L28 |
www.fairchildsemi.com
2
D
Functional Description
The two 8-bit shift registers have a common clock input
(pin 9) and separate clock inputs (pins 10 and 7). The
clocking of each register is controlled by the OR function of
the separate and the common clock input. Each register is
composed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW,
the slave latches are steady, but data can enter the master
latches via the R and S input. During the first LOW-to-
HIGH transition of either, or both simultaneously, of the two
clock inputs, the data inputs (R and S) are inhibited so that
a later change in input data will not affect the master; then
the now trapped information in the master is transferred to
the slave. When the transfer is complete, both the master
and the slave are steady as long as either or both clock
inputs remain HIGH. During the HIGH-to-LOW transition of
the last remaining HIGH clock input, the transfer path from
master to slave is inhibited first, leaving the slave steady in
its present state. The data inputs (R and S) are enabled so
that new data can enter the master. Either of the clock
inputs can be used as clock inhibit inputs by applying a
logic HIGH signal. Each 8-bit shift register has a 2-input
multiplexer in front of the serial data input. The two data
inputs D0 and D1 are controlled by the data select input (S)
following the Boolean expression:
Serial data in: S
D
=
SD0
+
SD1
An asynchronous master reset is provided which, when
activated by a LOW logic level, will clear all 16 stages inde-
pendently of any other input signal.
Shift Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
n
+
8
=
Indicates state after eight clock pulse
Logic Diagram
Inputs
D0
Output
Q7 (t
n
+
8
)
L
H
L
H
S
D1
L
L
H
H
L
H
X
X
X
X
L
H
相關PDF資料 |
PDF描述 |
|---|---|
| DM93L28N | Dual 8-Bit Shift Register |
| DM93L38 | 8-Bit Multiple Port Register(8位多端口寄存器) |
| DM93L38N | 8-Bit Multiple Port Register |
| DM93S62 | 9-Input Parity Checker/Generator |
| DM93S62N | 9-Input Parity Checker/Generator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM93L28N | 功能描述:計數器移位寄存器 Dual 8-Bit Shift Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM93L34 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L38 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:8-Bit Multiple Port Register |
| DM93L38N | 功能描述:寄存器 DISC BY MFG 7/03 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| DM93S41 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4-Bit Arithmetic Logic Unit |
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