參數(shù)資料
型號(hào): DM93L14N
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad Latch
中文描述: 93L SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP14
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-14
文件頁(yè)數(shù): 2/5頁(yè)
文件大?。?/td> 115K
代理商: DM93L14N
www.fairchildsemi.com
2
D
Functional Description
The DM93L14 consists of four latches with a common
active LOW Enable input and active LOW Master Reset
input. When the Enable goes HIGH, data present in the
latches is stored and the state of the latch is no longer
affected by the S
n
and D
n
inputs. the Master Reset when
activated overrides all other input conditions forcing all
latch outputs LOW. Each of the four latches can be oper-
ated in one of two modes:
D-TYPE LATCH—For D-type operation the S input of a
latch is held LOW. While the common Enable is active the
latch output follows the D input. Information present at the
latch output is stored in the latch when the Enable goes
HIGH.
SET/RESET LATCH—During set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the D
input, and can be set by a LOW on the S input if the D input
is HIGH. If both S and D inputs are LOW, the D input will
dominate and the latch will be reset. When the Enable
goes HIGH, the latch remains in the last state prior to dis-
ablement. The two modes of latch operation are shown in
the Truth Table.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Q
n
1
=
Previous Output State
Q
n
=
Present Output State
Logic Diagram
MR
H
H
H
H
H
H
H
H
L
E
L
L
H
L
L
L
L
H
X
D
L
H
X
L
H
L
H
X
X
S
L
L
X
L
L
H
H
X
X
Q
n
L
L
Q
n-1
L
H
L
Q
n-1
Q
n-1
L
Operation
D Mode
R/S Mode
RESET
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