參數(shù)資料
型號: DM93L08
文件頁數(shù): 97/158頁
文件大?。?/td> 2668K
代理商: DM93L08
Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 3 for waveforms and load configurations)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
t
PHL
Propagation Delay
En to Qn
45
38
ns
t
PLH
t
PHL
Propagation Delay
Dn to Qn
27
29
ns
t
PHL
Propagation Delay
MR to Qn
30
ns
Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW. As long as this logic condition exists, the
output of the latch will follow the input. If either of the enable
inputs goes HIGH, the data present in the latch at that time
is held in the latch and is no longer affected by data input.
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input.
Truth Table
MR
E0
E1
D
Qn
Operation
H
H
H
L
L
L
L
L
H
L
H
X
L
L
Data Entry
Data Entry
Hold
Qn
b
1
H
H
L
H
H
X
L
H
X
X
X
X
Qn
b
1
Qn
b
1
L
Hold
Hold
Reset
Q
n
b
1
e
Previous Output State
Q
n
e
Present Output State
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Logic Diagram
TL/F/9594–3
3
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