參數(shù)資料
型號(hào): DM9161A
廠商: Electronic Theatre Controls, Inc.
英文描述: 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述: 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁(yè)數(shù): 23/45頁(yè)
文件大小: 1206K
代理商: DM9161A
23
Preliminary
Version: DM9161A-DS-P04
Jan.19,2005
AD
D
00 CONTROL
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
Loop
back
0
TX FDX
Cap.
1
0
0
FLP Rcv
Ack
LP
Ack
Speed
select
1
TX HDX
Cap.
1
0
1
Remote
Fault
LP
RF
Auto-N
Enable
1
10 FDX
Cap.
1
0
1
Reserved
Power
Down
0
10 HDX
Cap.
1
0
1
Isolate
Restart
Auto-N
0
Full
Duplex
1
Coll.
Test
0
Reserved
0
T4
Cap.
0
0
1
Next
Page
LP
Next
Page
0
000_0000
Auto-N
Cap.
1
0
Reserved
Pream.
Supr.
1
0
Auto-N
Compl.
0
0
Remote
Fault
0
0
Link
Status
0
0
Version No.
0000
Jabber
Detect
0
0
Extd
Cap.
1
0
01
STATUS
0000
02
03
PHYID1
PHYID2
0
0
FC
Adv
LP
FC
0
1
1
Model No.
01010
TX HDX
Adv
LP
TX HDX
04 Auto-Neg.
Advertise
05
Link Part.
Ability
T4
Adv
LP
T4
TX FDX
Adv
LP
TX FDX
10 FDX
Adv
LP
10 FDX
10 HDX
Adv
LP
10 HDX
Advertised Protocol Selector Field
Reserved
Link Partner Protocol Selector Field
06 Auto-Neg.
Expansion
16 Specified
Config.
17 Specified
Conf/Stat
18
Conf/Stat
Reserved
Pardet
Fault
RPDCTR
-EN
LP Next
Pg Able
Reset
St. Mch
Next Pg
Able
Pream.
Supr.
Auto-N. Monitor Bit [3:0]
New Pg
Rcv
Sleep
mode
LP AutoN
Cap.
Remote
LoopOut
BP
4B5B
100
FDX
Rsvd
BP
SCR
100
HDX
LP
Enable
BP
ALIGN
10
FDX
HBE
Enable
BP_ADP
OK
10 HDX Reserve
Repeater
TX
FEF_EN RMII_E
N
Force
100LNK
TST_SE
L0
PHY ADDR [4:0]
LEDCO
L_SEL
d
Reverse
d
10T
Serial
Reverse
d
10T
SQUE
Enable
JAB
Enable
Reserved
Polarity
Reverse
19
PWDOR
Reserved
PD10DR
V
PD100l
PDchip
PDcrm
PDaeq
PDdrv
PDecli
PDeclo
PD10
20
Specified
config
TSTSE1 TSTSE2 FORCE_
TXSD
FORCE_
FEF
Reserved
MDIX_C
NTL
AutoNeg
_dlpbk
Mdix_fix
Value
Mdix_do
wn
MonSel1 MonSel0 Rmii_acc
u
PD_valu
e
21
MDINTR
Int_sts
Reserve
d
Reserve
d
Reverse
d
Fdx_msk Spd_msk Lnk_msk Int_msk Reserve
d
Reserve
d
Reverse
d
Fdx_chg Spd_chg Lnk_chg Reserve
d
Int_sts
22
RCVER
Receiver Error Counter
23 DIS_connec
t
Reversed
Disconnect_counter
24
RSTLH
Lh_led_
mode
Lh_mdint
r
Lh_cabst
s
Lh_isolat
e
Lh_rmii Lh_seril1
0
Lh_repea
ter
Lh_testm
ode
Lh_op2
Lh_op1
Lh_op0 Lh_phya
d4
Lh_phya
d3
Lh_phya
d2
Lh_phya
d1
Lh_phya
d0
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#)
Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
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