參數(shù)資料
型號: DM9102AT
廠商: Electronic Theatre Controls, Inc.
英文描述: Single Chip Fast Ethernet NIC controller
中文描述: 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁數(shù): 42/77頁
文件大?。?/td> 459K
代理商: DM9102AT
DM9102A
Single Chip Fast Ethernet NIC controller
42
Final
Version: DM9102A-DS-F03
August 28, 2000
Basic Mode Control Register (BMCR) – 0
Bit
0.15
Name
Reset
Default
0, RW/SC Reset:
Description
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers of the DM9102A to their
default states. This bit, which is self-clearing, will keep returning a value of one
until the reset process is completed
Loopback:
1=Loop-back enabled
0=Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead time" before
any valid data appear at the MII receive outputs
Speed Select:
1=100Mbps
0=10Mbps
Link speed may be selected either by this bit or by Auto-negotiation. When
Auto-negotiation is enabled and bit 12 is set, this bit will return Auto-
negotiation selected media type.
Auto-negotiation Enable:
1= Auto-negotiation enabled: bit 8 and 13 will be in Auto-negotiation status
0= Auto-negotiation disabled: bit 8 and 13 will determine the link speed and
mode
Power Down:
Setting this bit willpower down the whole chip except crystal / oscillator circuit.
1=Power Down
0=Normal Operation
Isolate:
1= Isolates the DM9102A from the MII with the exception of the serial
management.
0= Normal Operation
Restart Auto-negotiation:
1= Restart Auto-negotiation. Re-initiates the Auto-negotiation process. When
Auto-negotiation is disabled (bit 12 of this register cleared), this bit has no
function and it should be cleared. This bit is self-clearing and it will keep
returning a value of 1 until Auto-negotiation is initiated by the DM9102A. The
operation of the Auto-negotiation process will not be affected by the
management entity that clears this bit.
0= Normal Operation
Duplex Mode:
1= Full Duplex operation. Duplex selection is allowed when Auto-negotiation is
disabled (bit 12 of this register is cleared). With Auto-negotiation enabled, this
bit reflects the duplex capability selected by Auto-negotiation.
0= Normal operation
Collision Test:
1= Collision Test enabled. When set, this bit will cause the COL signal to be
asserted in response to the assertion of TX_EN.
0.14
Loopback
0, RW
0.13
Speed Selection
1, RW
0.12
Auto-negotiation
Enable
1, RW
0.11
Power Down
0, RW
0.10
Isolate
0,RW
0.9
Restart Auto-
negotiation
0,RW/SC
0.8
Duplex Mode
1,RW
0.7
Collision Test
0,RW
相關(guān)PDF資料
PDF描述
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
DM9108APPLICATIONENGINEERINGNOTESTWO DM9108 Application Engineering notes two
DM9161A 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
DM9161AE 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
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參數(shù)描述
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