參數(shù)資料
型號: DM9000AEP
廠商: Electronic Theatre Controls, Inc.
英文描述: Ethernet Controller with General Processor Interface
中文描述: 以太網控制器與通用處理器接口
文件頁數(shù): 46/56頁
文件大?。?/td> 1744K
代理商: DM9000AEP
DM9000A
Ethernet Controller with General Processor Interface
10.3 AC Electrical Characteristics & Timing Waveforms
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
46
10.3.1 TP Interface
Symbol
t
TR/F
t
TM
Parameter
Min.
3.0
0
Typ.
-
-
Max.
5.0
0.5
Unit
ns
ns
Conditions
100TX+/- Differential Rise/Fall Time
100TX+/- Differential Rise/Fall Time
Mismatch
100TX+/- Differential Output Duty Cycle
Distortion
100TX+/- Differential Output Peak-to-Peak
Jitter
100TX+/- Differential Voltage Overshoot
t
TDC
0
-
0.5
ns
T
t/T
0
-
1.4
ns
X
OST
0
-
5
%
10.3.2 Oscillator/Crystal Timing
Symbol
T
CKC
OSC Clock Cycle
T
PWH
OSC Pulse Width High
T
PWL
OSC Pulse Width Low
Parameter
Min.
39.998
16
16
Typ.
40
20
20
Max.
40.002
24
24
Unit
ns
ns
ns
Conditions
50ppm
10.3.3 Processor I/O Read Timing
T5
T1
T2
T6
IOR#
SD
T4
T3
CS#,CMD
IO16
T8
T7
Symbol
T
1
T
2
T
3
T
4
T
5
T
6
Parameter
Min.
0
10
0
2
Typ.
Max.
3
3
Unit
ns
ns
ns
ns
ns
clk*
CS#,CMD valid to IOR# valid
IOR# width
System Data(SD) Delay time
IOR# invalid to System Data(SD) invalid
IOR# invalid to CS#,CMD invalid
IOR# invalid to next IOR#/IOW# valid
When read DM9000A register
IOR# invalid to next IOR#/IOW# valid
When read DM9000A memory with F0h register
T
2
+T
6
IOR# invalid to next IOR#/IOW# valid
When read DM9000A memory with F2h register
T
7
CS#,CMD valid to IO16 valid
T
8
CS#,CMD invalid to IO16 invalid
*Note
(the default clk period is 20ns)
1. The IO16 is valid when the SD bus width is 16-bit
and the system address is DATA port (i.e. CMD is
T
6
4
clk*
1
clk*
3
3
ns
ns
high) and the value of INDEX port is memory data
register index.
ex. F0H, F2H, F6H or F8H
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