參數(shù)資料
型號(hào)： DM9000A
廠商： Electronic Theatre Controls, Inc.
英文描述： Ethernet Controller with General Processor Interface
中文描述： 以太網(wǎng)控制器與通用處理器接口
文件頁(yè)數(shù)： 18/56頁(yè)
文件大?。?/td> 1744K
代理商： DM9000A
DM9000A
Ethernet Controller with General Processor Interface
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
18
6.11 RX/TX Flow Control Register ( 0AH )
Bit
Name
Default
Description
7
TXP0
HPS0,RW
TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW of register 8.
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW of register 8.
HPS0,R/C RX Pause Packet Status, latch and read clearly
HPS0,RO
RX Pause Packet Current Status
Flow Control Enable
Set to enable the flow control mode (i.e. can disable DM9000A TX function)
6
TXPF
HPS0,RW
5
TXPEN
HPS0,RW
4
BKPA
HPS0,RW
3
BKPM
HPS0,RW
2
1
RXPS
RXPCS
0
FLCE
HPS0,RW
6.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
7:6
RESERVED
5
REEP
4
WEP
Default
0,RO
PH0,RW
PH0,RW
Description
Reserved
Reload EEPROM. Driver needs to clear it up after the operation completes
Write EEPROM Enable
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
3
EPOS
PH0,RW
2
ERPRR
PH0,RW
1
ERPRW
PH0,RW
0
ERRE
PH0,RO
6.13 EEPROM & PHY Address Register ( 0CH )
Bit
Name
Default
Description
7:6
PHY_ADR
PH01,RW
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 in
application.
EEPROM Word Address or PHY Register Number.
5:0
EROA
PH0,RW
6.14 EEPROM & PHY Data Register (EE_PHY_L 0DH EE_PHY_H 0EH)
Bit
Name
Default
EEPROM or PHY Low Byte Data
The low-byte data read from or write to EEPROM or PHY.
EEPROM or PHY High Byte Data
The high-byte data read from or write to EEPROM or PHY.
Description
7:0
EE_PHY_L
PH0,RW
7:0
EE_PHY_H
PH0,RW
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