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參數(shù)資料
| 型號： | DM9000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 575K |
| 代理商： | DM9000 |
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.13 EEPROM & PHY Address Register ( 0CH )
Bit
Name
Default
7:6
PHY_ADR
01,RW
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0
EROA
0,RW
EEPROM Word Address or PHY Register Address
Final
Version: DM9000-DS-F02
June 26, 2002
17
Description
6.14 EEPROM & PHY Data Register (EE_PHY_L
Bit
Name
7:0
EE_PHY_L
：
0DH EE_PHY_H
：
0EH)
Description
Default
X,RW
EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
7:0
EE_PHY_H
X,RW
6.15 Wake Up Control Register ( 0FH )
Bit
Name
7:6
RESERVED
5
LINKEN
Type
0,RO
0,RW
Description
Reserved
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
When set, it enables Magic Packet Wake up Event
This bit will not be affected after software reset
When set, it indicates that Link Change and Link Status Change Event occurred
This bit will not be affected after software reset
When set, it indicates that the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after software reset
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset
4
SAMPLEEN
0,RW
3
MAGICEN
0,RW
2
LINKST
0,RO
1
SAMPLEST
0,RO
0
MAGICST
0,RO
6.16 Physical Address Register ( 10H~15H )
Bit
Name
7:0
PAB5
7:0
PAB4
7:0
PAB3
7:0
PAB2
7:0
PAB1
7:0
PAB0
Default
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
Description
Physical Address Byte 5 (15H)
Physical Address Byte 4 (14H)
Physical Address Byte 3 (13H)
Physical Address Byte 2 (12H)
Physical Address Byte 1 (11H)
Physical Address Byte 0 (10H)
相關PDF資料 |
PDF描述 |
|---|---|
| DM9000E | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| DM9006CJ | Gate Expander |
| DM9006CN | Gate Expander |
| DM9009CJ | Dual 4-input NAND Gate |
| DM9009CN | Dual 4-input NAND Gate |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000()EVB | 制造商:DAVICOM 功能描述:BOARD EVALUATION DM9000 制造商:DAVICOM 功能描述:DM9000, MAC CNTLR, ENET, EVAL BOARD 制造商:DAVICOM 功能描述:EVAL BOARD, DM9000, MAC CNTLR, ENET; ;ROHS COMPLIANT: YES |
| DM9000_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:ISA to Ethernet MAC Controller with Integrated 10/100 PHY |
| DM9000A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface 臺灣Davicom公司出品的48pin、10/100M網(wǎng)絡控制芯片 |
| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9000AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface |
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