- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376788 > DM74LS194AM (FAIRCHILD SEMICONDUCTOR CORP) Octal Buffer/Line Driver with 3-STATE Outputs; Package: TSSOP; No of Pins: 20; Container: Rail PDF資料下載
參數(shù)資料
| 型號： | DM74LS194AM |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal Buffer/Line Driver with 3-STATE Outputs; Package: TSSOP; No of Pins: 20; Container: Rail |
| 中文描述： | LS SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 68K |
| 代理商： | DM74LS194AM |
2000 Fairchild Semiconductor Corporation
DS006407
www.fairchildsemi.com
August 1986
Revised March 2000
D
DM74LS194A
4-Bit Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; they feature parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-con-
trol inputs, and a direct overriding clear line. The register
has four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction Q
A
toward Q
D
)
Shift left (in the direction Q
D
toward Q
A
)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs,
S0 and S1, HIGH. The data is loaded into the associated
flip-flops and appear at the outputs after the positive transi-
tion of the clock input. During loading, serial data flow is
inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is HIGH and S1 is LOW.
Serial data for this mode is entered at the shift-right data
input. When S0 is LOW and S1 is HIGH, data shifts left
synchronously and new data is entered at the shift-left
serial input.
Clocking of the flip-flop is inhibited when both mode control
inputs are LOW.
Features
I
Parallel inputs and outputs
I
Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
I
Positive edge-triggered clocking
I
Direct overriding clear
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
DM74LS194AM
DM74LS194AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM74LS194AN | Octal Buffer/Line Driver with 3-STATE Outputs |
| DM74LS20 | Octal Buffer/Line Driver with 3-STATE Outputs |
| DM74LS20M | Octal Buffer/Line Driver with 3-STATE Outputs; Package: SOIC-Wide; No of Pins: 20; Container: Rail |
| DM74LS20N | Octal Buffer/Line Driver with 3-STATE Outputs; Package: SOIC-Wide; No of Pins: 20; Container: Tape & Reel |
| DM74LS20MX | Dual 4-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74LS194AMX | 功能描述:計(jì)數(shù)器移位寄存器 4-Bit Shift Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS194AN | 功能描述:計(jì)數(shù)器移位寄存器 4-Bit Shift Reg RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS197N | 制造商:National Semiconductor Corporation 功能描述: 制造商:Texas Instruments 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| DM74LS20 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS20M | 功能描述:邏輯門 Dl 4-Input NAND Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。