參數(shù)資料
型號: DM74LS166WM
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Quad Buffer with 3-STATE Outputs
中文描述: LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
封裝: 0.300 INCH, MS-013, SOIC-16
文件頁數(shù): 4/6頁
文件大?。?/td> 78K
代理商: DM74LS166WM
www.fairchildsemi.com
4
D
Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
Parameter Measurement Information
Voltage Waveforms
Test Table for Synchronous Inputs
Note A:
The clock pulse has the following characteristics: t
W(clock)
20 ns and PRR
=
1 MHz. The clear pulse has the following characteristics:
t
W(clear)
20 ns and t
HOLD
=
0 ns. When testing f
MAX
, vary the clock PRR.
Note B:
A clear pulse is applied prior to each test.
Note C:
Propagation delay times (t
PLH
and t
PHL
) are measured at t
n
+
1
. Proper shifting of data is verified at t
n
+
8
with a functional test.
Note D:
t
n
=
bit time before clocking transition
t
n
+
1
=
bit time after one clocking transition
t
n
+
8
=
bit time after eight clocking transitions
Note E:
V
REF
=
1.3V.
From (Input)
R
L
=
2 k
Symbol
Parameter
To (Output)
C
L
=
15 pF
Min
25
C
L
=
50 pF
Min
20
Units
Max
Max
f
MAX
t
PLH
Maximum Clock Frequency
Propagation Delay Time
MHz
Clock to Output
8
35
38
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
t
PHL
Clock to Output
8
35
41
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Clear to Output
6
30
36
ns
Data Input
for Test
H
Shift/Load
Output Tested
(See Note C)
Q
H
at T
N
+
1
Q
H
at T
N
+
8
0V
Serial Input
4.5V
相關(guān)PDF資料
PDF描述
DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register(8位并行輸入/串行輸出的移位寄存器)
DM74LS169 Quad Buffer with 3-STATE Outputs; Package: SOIC; No of Pins: 14; Container: Rail
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