
2–4
DLR/DLO/DLG1414
Figure 4. Block diagram
Character Set
3 2 1 0
Display
Rows 0 to 6
Timing and Control Logic
Row Control Logic
&
Row Drivers
Row Decoder
RAM Read Logic
RAM
Memory
ROM
128 X 35 Bit
ASCII
Character
Decode
7 Bit ASCII Code
Column Data
D
6
D
5
D
4
D
3
D
2
D
1
D
0
4480 bits
OSC
128
Counter
7
Counter
Column Enable
Latches and
Column Drivers
L
C
WR
A
0
A
1
Write
Address
4 X 7 bit
Columns 0 to 19
Decoder
ASCII
CODE
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
D6 D5 D4 HEX
1. High=1 level. 2. Low=0 level. 3. Upon power up, device will initialize in a random state.