參數(shù)資料
型號: DK-S6-EMBD-G
廠商: Xilinx Inc
文件頁數(shù): 2/11頁
文件大?。?/td> 0K
描述: DEV KIT EMBEDDED SPARTAN 6
產(chǎn)品培訓模塊: S6 Family Overview
標準包裝: 1
系列: Spartan®-6
類型: FPGA
適用于相關產(chǎn)品: Spartan?-6 FPGA,XC6SLX45T-FGG484
所含物品: 板,線纜,文檔,電源,軟件
其它名稱: 122-1688
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
10
Notice of Disclaimer
The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of
any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility
of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update.
You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to
the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to
warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or
for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical
03/03/10
1.4
Updated the slice counts for the LX25 and LX25T in Table 1. Revised the Dynamic Reconfiguration
Port section. Added to the Spread-Spectrum Clocking section. Changed the PLL VCO maximum
frequency to 1080 MHz and the DSP48A1 slice maximum frequency to 320 MHz due to the addition
of the -4 speed specification. Clarified configurations in the Programmable Data Width section.
Updated Low-Power Gigabit Transceiver operating rate.
08/02/10
1.5
Updated data transfer rate per differential I/O from 1,050 Mb/s to 1,080 Mb/s in Summary of Spartan-6
FPGA Features. Added the -3N speed grade to appropriate section throughout the document,
including Figure 1. Updated category in Table 2 from Size to Body Size. Updated the Configuration
section with SPI and BPI interface information. Removed the Dynamic Reconfiguration Port section.
Updated the operating speed of the DSP48A1 slice multiplier and accumulator to 390 MHz in Digital
11/05/10
1.6
transceiver data rate to 3.2 Gb/s. Updated the notes in Figure 1. Added
DS170, XA Spartan-6
Automotive FPGA Family Overview to the Spartan-6 FPGA Documentation.
03/21/11
1.7
Updated from Advance to Preliminary Specification. Removed -4 speed grade from Summary of
10/25/11
2.0
Updated from Preliminary Specification to Production Specification. Updated Configuration, including
the range of configuration bits to 3 Mb and 33 Mb, and Input and Output Delay. Updated Spartan-6
(DS172) to list of documentation.
Date
Version
Description of Revisions
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