參數(shù)資料
型號(hào)： DK-DEV-4SGX230N
廠商： Altera
文件頁(yè)數(shù)： 62/82頁(yè)
文件大?。?/td> 0K
描述： KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Stratix? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Stratix® IV GX
類(lèi)型： FPGA
適用于相關(guān)產(chǎn)品： EP4SGX230K
所含物品： 開(kāi)發(fā)板、通用電源、纜線和軟件
產(chǎn)品目錄頁(yè)面： 607 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱(chēng)： 544-2594
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–57
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–43 lists the DPA lock time specifications for Stratix IV ES devices.
Figure 1–4 shows the DPA lock time specifications with DPA PLL calibration enabled.
Table 1–43. DPA Lock Time Specifications—Stratix IV ES Devices Only (1), (2), (3)
Standard
Training Pattern
Number of Data
Transitions in
one repetition
of training
pattern
Number of
repetitions
per 256
data
transitions
Condition
Maximum
SPI-4
00000000001111111111
2
128
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Parallel Rapid
I/O
00001111
2
128
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
10010000
4
64
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Miscellaneous
10101010
8
32
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
01010101
8
32
without DPA PLL
calibration
256 data transitions
with DPA PLL
calibration
3x256 data transitions +
2x96 slow clock cycles (5)
Notes to Table 1–43
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time applies to commercial, industrial, and military speed grades.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = Data rate (Mbps)/Deserialization factor.
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_dpa_locked
rx_reset
DPA Lock Time
256 data
transitions
96 slow
clock cycles
256 data
transitions
256 data
transitions
96 slow
clock cycles
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DK-DEV-4SGX230N/C2 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過(guò)期 類(lèi)型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線纜，電源 標(biāo)準(zhǔn)包裝:1
DK-DEV-4SGX530N 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For EP4SGX530 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
DK-DEV-5AGTD7N 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For 5AGTD7K3F40I3N RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
DK-DEV-5AGXB3N/ES 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For 5AGXFB3H6F ES RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
DK-DEV-5ASTD5N 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件狀態(tài):在售 類(lèi)型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:Arria? V ST 內(nèi)容:板 標(biāo)準(zhǔn)包裝:1
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