
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
72
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Figure 30. Intel
LXT972M Transceiver MDIO Input Timing
Figure 31. Intel
LXT972M Transceiver MDIO Output Timing
Table 37. Intel
LXT972M Transceiver MDIO Timing
Parameter
Symbol
Min
Typ
1
Max
Units
Test Conditions
MDIO setup before MDC, sourced
by STA
t1
10
–
–
ns
–
MDIO hold after MDC, sourced by
STA
t2
5
–
–
ns
–
MDC to MDIO output delay,
sourced by PHY
t3
–
–
150
ns
–
MDC period
t4
125
–
–
ns
MDC = 8 MHz
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
testing.
t1
MDC
MDIO
t2
t3
MDC
MDIO
t4