
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
175
Table 54. Intel
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/-
5%)
Parameter
Sym
Min
Typ
1
Max
Units
Test Conditions
Input Low voltage
V
IL
–
–
0.8
V
–
Input High voltage
V
IH
2.0
–
–
V
–
Input current
I
I
-100
–
100
μ
A
0.0 < V
I
< V
CC
Output Low voltage
V
OL
–
–
0.2
V
I
OL
= 4 mA
Output Low voltage (LED
m
_
n
pins)
V
OL
-LED
–
–
0.5
V
I
OL
= 10 mA
Output High voltage
V
OH
2.4
–
–
V
I
OH
= -4 mA
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
Table 55. Intel
LXT9785/LXT9785E Digital I/O DC Electrical Characteristics – SD Pins
Parameter
Sym
Min
Typ
1
Max
Units
Test Conditions
2.5 V Operation
Input Low voltage
V
IL
0.69
0.8
1.03
V
VCCPECL = 2.5 V
Input High voltage
V
IH
1.34
1.6
1.62
V
VCCPECL = 2.5 V
3.3 V Operation
Input Low voltage
V
IL
1.49
1.6
1.83
V
VCCPECL = 3.3 V
Input High voltage
V
IH
2.14
2.4
2.42
V
VCCPECL = 3.3 V
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. For 2.5 V operation, SD_2P5V = VCCPECL and VCCPECL=2.5 V.
3. For 3.3 V operation, SD_2P5V = GNDPECL or Floating and VCCPECL=3.3 V.
Table 56. Intel
LXT9785/LXT9785E Required Clock Characteristics
Parameter
Sym
Min
Typ
2
Max
Units
Test Conditions
SMII Input frequency
f
–
125
–
MHz
–
RMII Input frequency
f
–
50
–
MHz
–
Input clock frequency tolerance
1
f
–
–
± 50
ppm
–
Input clock duty cycle
1
Tdc
35
50
65
%
RMII selection
Input clock duty cycle - REFCLK,
TxCLK
Tdc
40
50
60
%
SMII/SS-SMII selection
Output RxCLK duty cycle
Tdc
45
50
55
%
SS-SMII only
1. Parameter is guaranteed by design; not subject to production testing.
2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.