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      參數(shù)資料
      型號: DJIXP972MCEA4
      廠商: Intel Corp.
      英文描述: Single-Port 10/100 Mbps PHY Transceiver
      中文描述: 單端口10/100 Mbps的物理層收發(fā)器
      文件頁數(shù): 65/92頁
      文件大?。?/td> 666K
      代理商: DJIXP972MCEA4
      Intel
      LXT972M Single-Port 10/100 Mbps PHY Transceiver
      Datasheet
      Document Number: 302875-005
      Revision Date: 27-Oct-2005
      65
      7.2
      Timing Diagrams
      Figure 22. Intel
      LXT972M Transceiver 100BASE-TX Receive Timing
      Table 30. Intel
      LXT972M Transceiver 100BASE-TX Receive Timing Parameters
      Parameter
      Sym
      Min
      Typ
      1
      Max
      Units
      2
      Test Conditions
      RXD[3:0], RX_DV, RX_ER
      3
      setup to
      RX_CLK High
      t1
      10
      ns
      RXD[3:0], RX_DV, RX_ER hold
      from RX_CLK High
      t2
      10
      ns
      CRS asserted to RXD[3:0], RX_DV
      t3
      3
      5
      BT
      Receive start of “J” to CRS asserted
      t4
      12
      16
      BT
      Receive start of “T” to CRS de-asserted
      t5
      10
      17
      BT
      Receive start of “J” to COL asserted
      t6
      16
      22
      BT
      Receive start of “T” to COL de-asserted
      t7
      17
      20
      BT
      1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
      testing.
      2. BT (Bit Time) is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit
      rate. 100BASE-T bit time = 10
      -8
      s or 10 ns.
      3. RX_ER is not shown in the figure.
      t4
      t5
      t3
      t6
      t7
      0 ns
      250 ns
      CRS
      RX_DV
      RXD[3:0]
      RX_CLK
      COL
      t1
      t2
      TPI
      B3492-03
      Note: Timing diagram depicts 4B mode.
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