
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
179
Figure 40. Intel
LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing
Table 61. Intel
LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters
Parameter
Sym
Min
Typ
1
Max
Units
Test
Conditions
SYNC setup to REFCLK rising edge and
TxData setup to REFCLK rising edge
t1
1.5
–
–
ns
–
SYNC hold from REFCLK rising edge and
TxData hold from REFCLK rising edge
t2
1.0
–
–
ns
–
TxEN sampled to start of /J/
t3
–
11
18
BT
2
–
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
100BASE-TX or 100BASE-FX).
NOTE:
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TxData
TPFO
t
1
t
2
t
3
SYNC
t
1
t
2
REFCLK