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      參數(shù)資料
      型號: DJIXF972MECA4
      廠商: Intel Corp.
      英文描述: Single-Port 10/100 Mbps PHY Transceiver
      中文描述: 單端口10/100 Mbps的物理層收發(fā)器
      文件頁數(shù): 86/92頁
      文件大?。?/td> 666K
      代理商: DJIXF972MECA4
      Intel
      LXT972M Single-Port 10/100 Mbps PHY Transceiver
      86
      Datasheet
      Document Number: 302875-005
      Revision Date: 27-Oct-2005
      Table 53
      lists status change bits.
      Table 53. Status Change Register - Address 19, Hex 13
      Bit
      Name
      Description
      Type
      1
      Default
      19.15:9
      Reserved
      Ignore on Read.
      RO
      N/A
      19.8
      Reserved
      Ignore on Read.
      RO
      0
      19.7
      ANDONE
      Auto-negotiation Status
      0 = Auto-negotiation has not completed.
      1 = Auto-negotiation has completed.
      RO/
      SC
      N/A
      19.6
      SPEEDCHG
      Speed Change Status
      0 = A Speed Change has not occurred since last
      reading this register.
      1 = A Speed Change has occurred since last
      reading this register.
      RO/
      SC
      0
      19.5
      DUPLEXCHG
      Duplex Change Status
      0 = A Duplex Change has not occurred since last
      reading this register.
      1 = A Duplex Change has occurred since last
      reading this register.
      RO/
      SC
      0
      19.4
      LINKCHG
      Link Status Change Status
      0 = A Link Change has not occurred since last
      reading this register.
      1 = A Link Change has occurred since last reading
      this register.
      RO/
      SC
      0
      19.3
      Reserved
      Ignore on Read.
      RO
      0
      19.2
      Reserved
      Ignore on Read.
      RO
      0
      19.1
      Reserved
      Ignore on Read.
      RO
      0
      19.0
      Reserved
      Ignore on Read.
      RO
      0
      1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
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