- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376722 > DJIXELED0SE000 (Intel Corp.) Advanced 8-Port 10/100 Mbps PHY Transceivers PDF資料下載
參數(shù)資料
| 型號(hào)： | DJIXELED0SE000 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 160/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXELED0SE000 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)當(dāng)前第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
162
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
3. Poll Register bit 29.9. When this bit is set, the test is complete and Register bits 29.7:0 contain
a value used to determine if a cable fault was found and the distance to that fault. A value of
0xFFh indicates no fault was found. Any other value indicates a fault was found, that value
should be stored for later use.
4. Write 0x6C00h to Register 29. Setting these bits places the device in long cable Cable
Diagnostics mode.
5. Poll Register bit 29.9. When set, record the value of Register bits 29.7:0 if a fault is found.
6. If a fault is present, a calculation is used to determine the distance to the fault. Insert the
smallest value recorded from Register bits 29.7:0 in steps 3 and 5 above into the following
formula:
Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16
Register bit 29.8 is set if the fault is detected as a short circuit and is cleared if the fault is
detected as an open circuit. Register bits 29.12:11 are cleared when read and are cleared during
the same read cycle when Register bit 29.9 is read, indicating a fault condition exists.
7. Normal PHY operation can be resumed by writing 0x4000h to Register 29 or by software or
hardware reset. The test suite can be run again by resuming at step 2 above.
4.14
Link Hold-Off Overview
The PHY link is established as soon as the system platform powers-up. In many cases, the system
platform is not capable of supporting network operation until configuration firmware is loaded. It is
desirable in such cases to prevent the PHY from establishing a link until the system platform is
fully configured and ready for network operation. Link Hold-Off was incorporated into the
LXT9785 device to satisfy these requirements. Enabling Link Hold-Off disables the PHY Link
capability until the system platform is fully capable of supporting network operation. The feature is
enabled by hardware control at power-up or software control during normal operation.
4.14.1
Features
Link Hold-Off prevents the LXT9785 from establishing a link by disabling the analog transmit and
receive capability. The digital capabilities of the PHY are unaffected including register access and
LED operation. Link Hold-Off can be enabled by an external hardware pin for all ports or by
software register access for individual ports. When Link Hold-Off is enabled, the transmitter and
receiver on the selected ports are forced into software power-down mode (see
Section 4.5.3,
“Power-Down Mode” on page 127
) to block signal activity from establishing a link and passing
packets through the PHY.
The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-down
resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin enables the
feature at power-up reset or external hardware pin Reset. Once a PHY port is programmed as
desired, clearing Register bit 0.11 will re-enable that port. Each port must be individually re-
enabled.
When a port is software reset, by setting Register 0.15, the state of the hardware configuration pin
captured by the last hardware or power-up reset determines the default register values for the
specific function for that port. Link Hold-Off, once enabled by hardware configuration, is re-
enabled on a port by issuing a software reset for that port. It is not necessary to reset the entire PHY
or switch system to re-enable Link Hold-Off.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXELED0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXFLCD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXELED0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。