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參數資料
| 型號： | DJA |
| 廠商： | Lineage Power |
| 英文描述： | Digital Jitter Attenuation (DJA) Controller(數字信號抖動衰減控制器) |
| 中文描述： | 數字抖動衰減（DJA信息）控制器（數字信號抖動衰減控制器） |
| 文件頁數： | 1/2頁 |
| 文件大?。?/td> | 111K |
| 代理商： | DJA |
Product Brief
September 2000
Introduction
The digital jitter attenuator controller is a macrocell
block that is extractable from the TMXF28155 Super
Mapper application-specific standard product
(ASSP).
The DJA controller contains 28 DJA blocks. Each
DJA block can operate in two different modes, as a
DS1 or an E1 jitter attenuator. In both modes, the
DJA blocks can be provisioned to operate as a sec-
ond-order phase-locked loop (PLL) always, or it can
switch to act as a first-order PLL during virtual tribu-
tary (VT) pointer adjustments to help meet MTIE
requirements. The block will also insert the proper
alarm indication signal (AIS) if the primary block AIS
control input is active. The PLL bandwidth can be set
over a wide range to accommodate a number of dif-
ferent system constraints.
Features
The DJA block accepts/delivers DS1/E1 clock, data,
and AIS indications from/to the cross connect block.
I
AIS will cause the correct AIS clock to be inserted,
and the AIS indication will be passed back to the
cross connect.
I
The DJA blocks operate in the second-order PLL
mode under normal conditions. The DJA blocks
can be provisioned to enter the first-order PLL
mode following VT-level pointer adjustments. The
period of time in the first-order mode is provision-
able via registers.
I
The PLL bandwidth is provisionable between
0.1 Hz and 0.5 Hz. The damping factor for these
bandwidths varies between 2 Hz and 0.5 Hz.
Figure 1 shows the DJA block with I/O connections to
other blocks within the Super Mapper device.
5-8955 (F).a
Figure 1. DJA Block with I/O Connections to Other Blocks in the TMXF28155 Super Mapper
CROSS
CONNECT
MICRO INTERFACE
DIGITAL
JITTER
ATTENUATOR
XC_JDATA[28:1]
XC_JCLK[28:1]
XC_JPTRADJ[28:1]
XC_JAIS[28:1]
DJA_DATA[28:1]
DS1_AISCLK
E1_AISCLK
DJA_CLK[28:1]
E1_XCLK
DS1_XCLK
CONTROL
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