
E-50
DINK32 PowerPC ISA Debugger User’s Manual
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MOTOROLA
MPC8240 EPIC Interrupt Driver
{ EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source",
{ EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source",
{ EPIC_MSG_INT_VEC_REG, "Internal Message Source",
{ EPIC_DUART1_INT_VEC_REG, "DUART Ch1 Source",
{ EPIC_DUART2_INT_VEC_REG, "DUART Ch2 Source",
0x0},
0x0},
0x0}
0x0},
0x0}
};
Each of the 26 entries conforms to the following:
{
"vector/priority register address offset",
"text description",
"Interrupt Service Routine address"
}.
The first column of the structure contains the macro for each of the 26 interrupt
vector/priority register address offsets in EPIC. The middle column is the text description
of the interrupt vector, and the last column is the address of the registered interrupt service
routine (ISR) for each interrupt vector. Currently the structure is initialized such that each
vector ISR address is 0x0. This can be modified such that each defaults to a "catch all ISR"
address instead of 0x0. As each interrupt vector is set up, an ISR must be registered with
EPIC via the epicISRConnect() routine in the epic1.c source file. This routine takes the ISR
function name and stores the address of that function in the ISR Address structure location
corresponding to the interrupt vector number. Although each interrupt’s vector/priority
register allows the vector number to range from 0–255, this structure limits the vector
number range from 0–25. So as each interrupt's vector/priority register is set up, the 8-bit
vector field value must match the vector number location in the structure.
E.4.5
EPIC Sample Routines
The EPIC sample routines are contained in the epic1.c and epic2.s files. All C language
routines are in epic1.c and all assembly language routines are in epic2.s. These routines,
along with the structure described in E.4.4, “EPIC Cross-Reference Table Structure, can be
used as sample code for systems using the EPIC Unit. E.4.6, “EPIC Commands in DINK32
describes how these routines are used by DINK32.
E.4.5.1
Low-Level Routines
The following routines are in the epic2.s source file:
External Interrupt Control Routines:
— CoreExtIntEnable(): enables external interrupts by setting the MSR[EE] bit
— CoreExtIntDisable(): disables external interrupts by clearing the MSR[EE] bit
Low Level Exception Handler:
— epic_exception():
Save the current (interrupted) programming model/state
Calls epicISR() to service the interrupt
F
n
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